org 0x0

start:
;no ac,cy,ov
    MOV A,#0x36
	ADD A,#0x12
	MOV 0x20,PSW
	MOV 0x21,A
	
	;cy
	MOV A,#0xc6
	ADD A,#0xC3
	MOV 0x22,PSW
	MOV 0x23,A
	
	;ac
	MOV A,#0x19
	ADD A,#0x2E
	MOV 0x24,PSW
	MOV 0x25,A
	
	;ov, bit6->bit7
	MOV A,#0x48
	ADD A,#0x72
	MOV 0x26,PSW
	MOV 0x27,A
	;ov+cy bit7->bit8
	mov a,#0xc8
	add a,#0xa2
	mov 0x28,psw
	mov 0x29,a
	;ov, cy, ac
	mov a,#0xc8
	add a,#0xa8
	mov 0x2a,psw
	mov 0x2b,a
	
	sjmp $
;for test
REG_SP     EQU 0x1000
REG_A      EQU 0x1001
REG_B      EQU 0x1002
REG_PSW    EQU 0x1003
REG_PC     EQU 0x1004
REG_DPTR   EQU 0x1005
CYCLE      EQU 0x1006
REG_R0     EQU 0x2000
REG_R1     EQU 0x2001
REG_R2     EQU 0x2002
REG_R3     EQU 0x2003
REG_R4     EQU 0x2004
REG_R5     EQU 0x2005
REG_R6     EQU 0x2006
REG_R7     EQU 0x2007
REG_END    EQU 0x2FFF
	org 0x600
	dw 0x20,0x00
	dw 0x21,0x48
	dw 0x22,0x81
	dw 0x23,0x89
	dw 0x24,0x40
	dw 0x25,0x47
	dw 0x26,0x05
	dw 0x27,0xba
	dw 0x28,0x84
	dw 0x29,0x6a
	dw 0x2a,0xc5
	dw 0x2b,0x70
		
	dw REG_SP,    0x7
	dw REG_A,     0x70
	dw REG_B,     0x0
	dw REG_PC,    0x36
	dw REG_DPTR,  0x0
	dw CYCLE,     32
	dw REG_R0,    0x0
	dw REG_R1,    0x0
	dw REG_R2,    0x0
	dw REG_R3,    0x0
	dw REG_R4,    0x0
	dw REG_R5,    0x0
	dw REG_R6,    0x0
	dw REG_R7,    0x0
	dw REG_END
end
	